`timescale 1ns/1ps
//in wrapper ,all control signals active high

module ram_2p_d4096_w48_wrapper (clk,wren,waddr,wdata,rden,raddr,ram_2p_cfg_register,rdata);
  input  clk;
  input [5:0] wren;//write enable,active high 
  input [11:0] waddr;//waddr
  input [47:0] wdata;//wdata
  input [5:0] rden;//read enable,active high
  input [11:0] raddr;//raddr
  input [9:0] ram_2p_cfg_register;
  output [47:0] rdata;//rdata

wire [7:0] rdata0,rdata1,rdata2,rdata3,rdata4,rdata5;

assign rdata = {rdata5,rdata4,rdata3,rdata2,rdata1,rdata0};

ram_2p_d4096_w8 U0_ram_2p_d4096_w8 ( 
.QA(rdata0), 
.CLK(clk), 
.CENA(~rden[0]),//read enable,active low 
.CENB(~wren[0]),//write enable,active low
.AA(raddr), 
.AB(waddr), 
.DB(wdata[7:0]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);

ram_2p_d4096_w8 U1_ram_2p_d4096_w8 ( 
.QA(rdata1), 
.CLK(clk), 
.CENA(~rden[1]),//read enable,active low 
.CENB(~wren[1]),//write enable,active low
.AA(raddr), 
.AB(waddr), 
.DB(wdata[15:8]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);

ram_2p_d4096_w8 U2_ram_2p_d4096_w8 ( 
.QA(rdata2), 
.CLK(clk), 
.CENA(~rden[2]),//read enable,active low 
.CENB(~wren[2]),//write enable,active low
.AA(raddr), 
.AB(waddr), 
.DB(wdata[23:16]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);

ram_2p_d4096_w8 U3_ram_2p_d4096_w8 ( 
.QA(rdata3), 
.CLK(clk), 
.CENA(~rden[3]),//read enable,active low 
.CENB(~wren[3]),//write enable,active low
.AA(raddr), 
.AB(waddr), 
.DB(wdata[31:24]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);

ram_2p_d4096_w8 U4_ram_2p_d4096_w8 ( 
.QA(rdata4), 
.CLK(clk), 
.CENA(~rden[4]),//read enable,active low 
.CENB(~wren[4]),//write enable,active low
.AA(raddr), 
.AB(waddr), 
.DB(wdata[39:32]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
);

ram_2p_d4096_w8 U5_ram_2p_d4096_w8 ( 
.QA(rdata5), 
.CLK(clk), 
.CENA(~rden[5]),//read enable,active low 
.CENB(~wren[5]),//write enable,active low
.AA(raddr), 
.AB(waddr), 
.DB(wdata[47:40]), 
.STOV(ram_2p_cfg_register[9]), 
.STOVAB(ram_2p_cfg_register[8]), 
.EMA(ram_2p_cfg_register[7:5]), 
.EMAW(ram_2p_cfg_register[4:3]),
.EMAS(ram_2p_cfg_register[2]), 
.EMAP(ram_2p_cfg_register[1]), 
.RET1N(ram_2p_cfg_register[0])
); 
endmodule
